3*3 乘法機 執行圖

除法機改乘法機的程式碼

`define NUM_STATE_BITS 3
`define IDLE 3'b000
`define COMPUTE 3'b001

//`include "clock.v"

module slow_div_system(pb,ready,x,y,r3,sysclk);
input pb,x,y,sysclk;
output ready,r3;
wire pb;
wire [11:0] x,y;
reg ready;
reg [11:0] r1,r2,r3;
reg [`NUM_STATE_BITS-1:0] present_state;

always
begin
@(posedge sysclk) enter_new_state(`IDLE);
r1 <= @(posedge sysclk) x;
r2 <= @(posedge sysclk) 0;
ready = 1;
if (pb)
begin
while (r1 >=1 | pb)
begin
@(posedge sysclk) enter_new_state(`COMPUTE);
r1 <= @(posedge sysclk) r1 - 1;
r2 <= @(posedge sysclk) r2 + y;
r3 <= @(posedge sysclk) r2;
end
end
end

task enter_new_state;
input [`NUM_STATE_BITS-1:0] this_state;
begin
present_state = this_state;
#1 ready=0;
end
endtask

always @(posedge sysclk) #20
$display("%d r1=%d r2=%d r3=%d pb=%b ready=%b", $time, r1,r2,r3, pb, ready);
endmodule


module top;
reg pb;
reg [11:0] x,y;
wire [11:0] quotient;
wire ready;
integer s;
wire sysclk;

cl #20000 clock(sysclk);
slow_div_system slow_div_machine(pb,ready,x,y,quotient,sysclk);

initial
begin
pb= 0;
x = 3;
y = 3;
#250;
@(posedge sysclk);

begin
@(posedge sysclk);
pb = 1;
@(posedge sysclk);
pb = 0;
@(posedge sysclk);
wait(ready);
@(posedge sysclk);
if (x*y === quotient)
$display("ok");
else
$display("error x=%d y=%d x*y=%d quotient=%d",x,y,x*y,quotient);
end
$stop;
end
endmodule





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哇 努力了好久終於通過考試了　感覺好像很難的樣子　　不過融會貫通後就覺得沒有那麼難了
被問了好幾次　　不過終於通過啦


module cl(clk);
parameter TIME_LIMIT = 110000; //1250;
output clk;
reg clk;

initial
clk = 0;

always
#50 clk = ~clk;

always @(posedge clk)
if ($time > TIME_LIMIT) #70 $stop;

endmodule

　　　
上面程式為ｃｌｏｃｋ程式碼